ASIC Design Verification Engineer

Who We Are:

The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web-scale data centers and across service providers, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing, and testing some of the most complex ASICs being developed in the industry.

Who You'll Work With:

You will be in the Silicon One development organization as an ASIC design verification engineer in San Jose, CA. You collaborate closely with verification engineers, designers, hardware and cross-functional teams to verify the ASIC in simulation, in emulation, and during ASIC bring-up.

What You'll Do:

• Maintaining existing DV environments and enhancing them
• Construct testbench including scoreboard, agents, sequencers, and monitors for new blocks
• Write test plan, develop testcases, debug regression failures and drive to module verification closure
• Ensuring complete verification coverage through implementation and review of code and functional coverage

Minimum Qualifications:

• Bachelor's or Master's degree and 8 years of relevant experience required; prior experience with System Verilog and UVM methodology
• Prior experience in verifying complex blocks, clusters and top level for SoC
• Prior experience building testbenches from scratch, hands on experience with System Verilog constraints, structures and classes.
• Prior experience with functional coverage and constrained random DV environments.
• Scripting skills: Perl and/or Python scripting

Preferred Qualifications:

• Strong domain experience on one or more protocols in a plus - PCIe, CXL, Ethernet, AHB/AXI, DDR, MMU.
• Experience with Veloce/HAPS is a plus
• Formal verification (iev/vc formal) knowledge is a plus