Senior Staff Static Timing Analysis & Physical Design Engineer

About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

What You Can Expect

This role is based in the Marvell office in Boise, ID. You will work with both local and global STA team members on the timing analysis and timing closure of complex chips, as well as the methodology to enable an efficient and robust design process.

Key responsibilities include:

• Work with teams across various disciplines such as PD/Digital/RTL/Analog to ensure design convergence and integration in a timely manner.

• Perform Static Timing Analysis and design timing convergence and closure on multi-voltage designs using industry standard EDA tools (PrimeTime preferred).

• Work with RTL design teams to drive assembly and design closure.

• Collaborate with physical design engineers to drive designs to timing closure.

• Provide technical direction, coaching, and mentoring to junior employees and colleagues when necessary to achieve successful project outcomes.

• Write scripts in Shell, Python, and TCL to extract data and achieve productivity enhancements through automation.

What We're Looking For

Basic Qualifications:

• Bachelor's Degree in Electrical/Computer Engineering plus 3-5 years of related experience, OR a Master's Degree in Electrical/Computer Engineering with 2-3 years related experience.

• Expertise in full-chip & sub-hierarchy integration.

• Experience integrating and taping out large designs utilizing a digital design environment.

• Good understanding of RTL to GDS flows and methodology.

• Good scripting skills in TCL/Python.

• Knowledge of Verilog.

Preferred Qualifications:

• Static Timing Analysis familiarity or experience.

• Expertise in Static Timing Analysis using industry-standard STA tools (PrimeTime preferred).

• Experience driving timing closure and taping out large designs utilizing a digital design environment.

• Experience with advanced Clock Tree Synthesis and Analysis techniques.

• Experience closing timing in a Tessent DFT based design is a plus.

• Experience with Cadence Innovus.

• Experience with PrimeTime.

Expected Base Pay Range (USD)

The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.