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Principal Engineer, Physical Design

Marvell Semiconductor, Inc.
United States, California, Santa Clara
5488 Marvell Lane (Show on map)
May 16, 2025

About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

Built on decades of expertise and execution, Marvell's custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual property (IP) and a wide array of flexible business models. In this unique role, you'll have the opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance processor chips in a leading-edge CMOS process technology, targeted at server, 5G/6G, automotive, and networking applications.

What You Can Expect

Perform complex custom Block Level Synthesis and block floorplan. Work closely with full chip teams, Static Timing Analysis STA team, and block owners to develop Marvell Switch devices layout till Tape-out. Own initial spec development, implementation, signoff, and delivery of blocks and components that go into our advanced switch products. Build customized clock structure. Own block level Place and Route implementation for multiple Switch BU blocks. Work closely with physical verification, timing, and power network integrity signoff checks to ensure blocks meet rigorous QoR requirements. Work with flow teams to develop and deploy updates for new projects and processes. Wage $205,000.000 - $215,000.00. Telecommuting is permitted.

What We're Looking For

Bachelor's or foreign equivalent degree in Electrical/Electronic Engineering, Computer Science/Engineering, or a related field and five (5) years of experience in the job offered or related occupation.

Experience must include five (5) years with each of the following:

* Physical Design implementation of complex blocks from RTL to GDS/ Oasis.
* Advanced process nodes (5nm and 3nm).
* Place and Route tools such as Innovus and ICC2.
* Signoff physical verification, block level STA, and EMIR analysis.
* Synthesis, Physical Design, and Timing Closure.
* Floorplanning with emphasis on timing and routability convergence.
* Clock tree synthesis and setup/ hold timing considerations.
* Dynamic and leakage power optimization strategies.
* TCL scripting.

Additional Compensation and Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We're dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it's like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

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