Principal Physical Design Engineer

About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

What You Can Expect

• In this onsite role, you will be the leader on a large complex chip/sub-system/partition through all phases of the design
• Responsible for floorplanning a chip/sub-system/partition, pushing down block boundary and pin assignment to team members
• Work with a variety of teams to pull in their required portion of the sub-system, such as DFT and clock distribution teams
• Leading a small group of engineers at the block level, ensuring they are progressing, meeting milestones on schedule and quality, and correct deliverables

• Work closely with the block level PD engineers in debugging and resolving timing and routing issues across all hierarchical levels

• Be an active team member on physical design methodology
• Provide technical direction, coaching, and mentoring to employees on your team and others when necessary to achieve successful project outcomes

• Write scripts in Perl, Python and TCL to extract data and achieve productivity enhancements through automation

What We're Looking For

To be successful in this role you must:

• BS in EE/CE/CS with 10+ years of experience, or MS in EE/CE/CS with 5+ years of experience
• 5 years of practical experience in physical design at all levels of hierarchy with multiple ASICs/SOCs
• Physical design knowledge and experience, from RTL or netlist handoff to GDS tape-out
• Extensive experience with floorplanning at a sub-system/partition level, considering boundary snap of power/technology and pin assignment
• Proficient in running chip/sub-system/partition level signoff, including physical verification (DRC and LVS), along with power integrity (EMIR)
• Experienced in leading a team of block-level engineers, coordinating at the sub-system/partition level
• Good knowledge of Verilog/VHDL, and track record of collaboration with RTL team
• Good understanding of digital logic and architecture
• Proficient in LINUX and shell-based scripting
• Knowledge and experience with TCL language
• Diligent, detail-oriented, and able to handle assignments with minimal supervision
• Must possess good communication skills, be a self-driven individual, and a good team player

Expected Base Pay Range (USD)

The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.