New

Design for Test Engineering Intern - Bachelors Degree

Marvell Semiconductor, Inc.
paid holidays, sick time
United States, Massachusetts, Westborough
Sep 18, 2025
About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Marvell embedded processors are custom designed to deliver optimal performance, low power, and high levels of integration. The Marvell ARMv7 compliant CPU cores are the most advanced implementations of the industry standard ARM architecture and deliver exceptional processing performance at low power. Advanced system architecture design and years of experience in sub-micron mixed signal technology seamlessly implement processor cores with our wide selection of high speed interfaces to precisely meet the needs of each application. Will work with a world class Design For Test (DFT) team solving the latest industry challenges in bringing our large SoC product offerings to volume manufacturing. DFT group is involved in all aspects of design and development of custom solutions in RTL & Verification that provide better manufacturing solutions for our complex offerings. Group is also responsible for brining products to volume manufacturing. What You Can Expect Develop understanding of the block level or chip top design-for-test (DFT) and automated test pattern generation (ATPG) flows for complex SOC designs Execute DFT insertion and verification flows for scan test, Memory Built-in Self-Test (MBIST), and IP macro test Execute digital logic, MBIST, and IP test pattern generation and simulation flows Analyze results and look for ways to improve test coverage Collaborate with the global DFT team on design flow improvements What We're Looking For Currently pursuing a Bachelor's degree in Computer Science, Electrical Engineering, or related fields Good understanding of digital logic design using Verilog/System Verilog Knowledge of JTAG standards and boundary scan implementation Knowledge of Scan test, memory BIST/BISR, functional test, JTAG, and other test methodologies is a plus Experience in programming and scripting languages such as Python, Perl, Tcl Good understanding of Linux/Unix, with experience working on distributed systems Effective teamwork and communication skills Expected Base Pay Range (USD) 31 - 61, $ per hour. The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions. Additional Compensation and Benefit Elements For Internship roles, we are proud to offer the following benefits package during the internship - medical, dental and vision coverage, perks and discount programs, wellness & mental health support including coaching and therapy, paid holidays, paid volunteer days and paid sick time. Additional compensation may be available for intern PhD candidates. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com. *Interview Integrity* As part of our commitment to fair and authentic hiring practices, we ask that candidates do not use AI tools (e.g., transcription apps, real-time answer generators like ChatGPT, CoPilot, or note-taking bots) during interviews. Our interviews are designed to assess your personal experience, thought process, and communication skills in real-time. If a candidate uses such tools during an interview, they will be disqualified from the hiring process. This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment. #LI-LM1