Hardware & Silicon Validation Senior Staff Engineer

About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

What You Can Expect

* Own the endtoend validation strategy for DDR and HBM subsystems, from presilicon planning through postsilicon bringup, characterization, and production readiness.
* Define validation scope, coverage metrics, and test methodologies for memory controllers, PHYs, and full memory subsystems, ensuring compliance with JEDEC specifications and internal quality standards.
* Lead postsilicon bringup and debug of complex memory systems, driving rootcause analysis across silicon, firmware, signal integrity, power integrity, and test infrastructure domains.
* Serve as the primary technical authority for DDR and HBM validation, providing guidance on architecture tradeoffs, risk mitigation, and design optimization.
* Drive crossfunctional collaboration with architecture, RTL, PHY, SI/PI, firmware, system validation, and product engineering teams to resolve issues and influence design improvements.
* Lead development and execution of stress, cornercase, performance, and RAS testing across PVT conditions to ensure longterm reliability and robustness.
* Partner with firmware and software teams to define and validate training algorithms, diagnostics, error handling, and recovery mechanisms.
* Present technical findings, risk assessments, and validation status to engineering leadership and program stakeholders, enabling datadriven decision making.
* Actively influence best practices in validation methodology, automation, and lab infrastructure, helping scale validation efficiency for future silicon generations.
* Support customerfacing debug and escalations when required, providing expertlevel analysis and guidance on memoryrelated issues.

What We're Looking For

* Bachelor's degree in Computer Science, Electrical Engineering, or a related field with 5-10 years of relevant industry experience; or Master's degree and/or PhD in Computer Science, Electrical Engineering, or a related discipline with 3-5 years of professional experience.
* Deep handson expertise in DDR memory technologies including DDR4, DDR5 and LPDDR4/5, covering protocol, timing, training, power management, and systemlevel behavior.
* Background in HBM (HBM2 / HBM2E / HBM3 / HBM4 / HBM4E) architecture and validation, including stack integration, memory controllers, PHY interaction, bringup, and performance characterization is strongly preferred.
* Expert understanding of memory subsystem architecture, including controller, PHY, interconnect, training algorithms, error handling (ECC), and RAS features.
* Extensive experience validating JEDEC memory standards, interpreting specifications, and ensuring compliance across process, voltage, temperature (PVT) corners.
* Demonstrated expertise in postsilicon bringup, validation, stress testing, and debug of memory subsystems at block, subsystem, and fullchip levels.
* Handson experience with highspeed lab equipment, including oscilloscopes, logic analyzers, protocol analyzers, and memory test platforms.
* Proficiency in C/C++ for embedded or baremetal firmware development to support memory bringup, training, diagnostics, and stress testing.
* Strong experience developing Pythonbased automation frameworks for functional, regression, stress, and manufacturing validation.
* Experience leading validation strategy and test planning for DDR and HBM subsystems, including coverage definition and execution ownership.
* Excellent written and verbal communication skills, with the ability to present technical findings clearly to engineering leadership and executive stakeholders.
* Hands-on wafer probe experience operating wafer probers, probe cards and automated test equipment(ATE) along with understanding of wafer-level test flow is preferred.

* Strong debugging skills using JTAG, boundary scan and trace tools is preferred.

Expected Base Pay Range (USD)

The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.