Principal Digital IC Design Engineer

About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

What You Can Expect

• Define and drive micro-architecture and RTL implementation for complex functional blocks in custom AI accelerators, CPUs, or high-speed interconnect silicon, working in advanced process nodes (3nm, 2nm) to meet aggressive performance, power, and area (PPA) targets
• Own end-to-end delivery of assigned blocks or subsystems from architecture definition through tape-out, including synthesis, timing closure, formal verification, and physical verification sign-off
• Collaborate closely with cross-functional teams including verification engineers on test plan development and coverage analysis, physical design teams on floorplanning and timing optimization, and DFT teams on scan insertion and test pattern generation
• Drive timing and power closure for high-speed designs (>1 GHz), working with implementation teams to resolve congestion issues, develop timing ECOs, and optimize critical paths to achieve sign-off quality
• Partner with customer architects and engineers to translate application requirements into hardware specifications, participate in design reviews, and support technical discussions throughout the development cycle
• Integrate and validate third-party IP (PCIe, CXL, DDR, SerDes, etc.) within the SoC, ensuring interoperability and compliance with industry standards while meeting customer-specific performance requirements
• Support post-silicon validation and bring-up activities, including debugging silicon issues, correlating RTL simulations with lab measurements, and working with validation teams to resolve production issues
• Contribute to methodology development by improving design flows, developing automation scripts, and establishing best practices that enhance productivity across global design teams
• Present technical work and design trade-offs to stakeholders through design reviews, architecture discussions, and cross-functional team meetings, maintaining clear documentation throughout the development cycle

What We're Looking For

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field with 10+ years of professional experience in digital IC design, OR Master's degree with 5+ years of experience
• Proven RTL design experience with expertise in synthesis, static timing analysis and closure, formal verification, and gate-level simulations
• Proficiency with design quality checks including Lint, CDC (Clock Domain Crossing), RDC (Reset Domain Crossing), and logic equivalence checking (LEC)
• Strong foundation in modern SoC architectures and industry-standard interface protocols including AXI, DDR, Ethernet, and PCIe
• Experience with low-power design methodologies including clock gating, power gating, and UPF (Unified Power Format) implementation
• Hands-on experience with the full chip development lifecycle, from micro-architecture definition through physical implementation

Preferred Qualifications

• Micro-architecture design experience in one or more specialized domains: AI/ML accelerators, embedded processors, DSP engines, graphics processors, or general-purpose compute cores
• Familiarity with high-performance interconnect technologies such as SerDes, CXL, or die-to-die interfaces
• Proficiency in scripting and automation using Python, Perl, Tcl, or shell scripting to improve design productivity

Expected Base Pay Range (USD)

The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.